Volume 55, Number 2, July 2001
|Page(s)||253 - 259|
|Section||Interdisciplinary physics and related areas of science and technology|
|Published online||01 December 2003|
Modelling background charge rearrangements near single-electron transistors as a Poisson process
Solid-State Physics Laboratory, ETH Zürich -
CH-8093 Zürich, Switzerland
2 Integrated Systems Engineering, ISE - CH-8008 Zürich, Switzerland
3 Swiss Federal Office of Metrology and Accreditation, METAS CH-3003 Bern-Wabern, Switzerland
Corresponding author: firstname.lastname@example.org
Accepted: 3 May 2001
Background charge rearrangements in metallic single-electron transistors are modelled in two-level tunnelling systems as a Poisson process with a scale parameter as only variable. The model explains the recent observation of asymmetric Coulomb blockade peak spacing distributions in metallic single-electron transistors. These distributions are consistent with charge trapping processes within impurities located between transistor island and gate. From the scale parameter determined, we estimate the average size of the tunnelling systems, their density of states, and the height of their energy barrier.
PACS: 73.23.Hk – Coulomb blockade; single-electron tunnelling / 73.50.Gr – Charge carriers: generation, recombination, lifetime, trapping, mean free paths / 02.50.Ey – Stochastic processes
© EDP Sciences, 2001
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