Issue |
EPL
Volume 99, Number 5, September 2012
|
|
---|---|---|
Article Number | 57004 | |
Number of page(s) | 6 | |
Section | Condensed Matter: Electronic Structure, Electrical, Magnetic and Optical Properties | |
DOI | https://doi.org/10.1209/0295-5075/99/57004 | |
Published online | 12 September 2012 |
Ground-state spin logic
1 Department of Physics, Columbia University - 538 W. 120th St, New York, NY 10027, USA
2 Institute for Scientific Interchange - Via Alassio 11/c, 10126 Torino, Italy, EU
3 Quantum Information Technologies, NEC Laboratories America - 4 Independence Way, Princeton, NJ 08540, USA
4 Centre for Quantum Technologies, National University of Singapore - Block S15, 3 Science Drive 2, Singapore 117543
(a) Current address: Vienna Center for Quantum Science and Technology - Boltzmanngasse 5, 1090 Vienna, Austria, EU; james.whitfield@univie.ac.at
(a) Current address: Vienna Center for Quantum Science and Technology - Boltzmanngasse 5, 1090 Vienna, Austria, EU; jdwhitfield@gmail.com
(b) mauro.faccin@isi.it
(c) jacob.biamonte@qubit.org
Received: 7 May 2012
Accepted: 6 August 2012
Designing and optimizing cost functions and energy landscapes is a problem encountered in many fields of science and engineering. These landscapes and cost functions can be embedded and annealed in experimentally controllable spin Hamiltonians. Using an approach based on group theory and symmetries, we examine the embedding of Boolean logic gates into the ground-state subspace of such spin systems. We describe parameterized families of diagonal Hamiltonians and symmetry operations which preserve the ground-state subspace encoding the truth tables of Boolean formulas. The ground-state embeddings of adder circuits are used to illustrate how gates are combined and simplified using symmetry. Our work is relevant for experimental demonstrations of ground-state embeddings found in both classical optimization as well as adiabatic quantum optimization.
PACS: 75.10.Dg – Crystal-field theory and spin Hamiltonians / 03.65.Fd – Algebraic methods / 84.30.Bv – Circuit theory
© EPLA, 2012
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