Estimation of interfacial-layer thickness from voltage-dependent domain switching times in LiNbO₃ single-crystal domain wall memory

State Key Laboratory of ASIC & System School of Microelectronics, Fudan University - Shanghai 200433, China

^(a) E-mail: aqjiang@fudan.edu.cn (corresponding author)

Received: 10 November 2022
Accepted: 2 January 2023

Abstract

Conducting domain walls created through the local domain 180° reversal within LiNbO₃ mesa-like cells fabricated at the surface of a single-crystal LiNbO₃ thin film have enabled ferroelectric domain wall memories, transistors, and sensors, where volatile switching in the domains within the interfacial layers near two side electrodes can rectify diode-like wall conduction under an applied voltage higher than an onset voltage. The diodes at interfaces not only can perform NOT, NAND, and NOR gate logic functions for in-memory computing, but can also work as embedded selectors for the fabrication of crossbar arrays of the memories in adjustable onset voltages that are proportional to the thicknesses of interfacial layers. Here, we develop a method to estimate the interfacial-layer thickness through the measurements of voltage-dependent domain switching times across two interfacial layers and an entire memory cell, respectively. Both dependences can be fitted according to the Merz law using an identical activation field from which we derived the equivalent electrical thickness of the interfacial layer. This non-destructive estimation paves the way to tailoring onset voltages of the diodes through the regulation of interfacial-layer thicknesses within various domain wall nanodevices.